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The world's first hybrid x86-compatible architecture has been released
2018-12-15T19:52:40.438Z15 December 2018

The world's first hybrid x86-compatible architecture has been released

Head of Core and Visual Computing Group presented the world's first hybrid x86-compatible micro-architecture. It sounds too hastily, but it looks interesting and promising. In fact, Koduri spoke about a new 3D-packaging of diverse crystals into a single, but compact solution. In fact, we see the development of the idea of multi-chip packaging, which was previously implemented by the company in the form of EMIB packaging. But if EMIB was a budget equivalent of a 2.5D package, then the new 3D package takes Intel far ahead in relation to the multi-chip products of the same AMD and NVIDIA.

Like AMD, Intel refers to individual crystals as chiplets. The resulting hybrid chip is assembled from several chiplets, each of which can be released in its own process technology with any technological standards. Chiplets are soldered on a bridge, but Intel says it is necessary to go further. The bridge must be active. It must contain bus control circuits for connecting chiplets and must compensate for attenuation and ensure line matching.

Most interesting is that Intel is preparing to release solutions in a new package in less than a year, namely in the second half of 2019. Technology got the name Foveros. As a demonstration, Koduri showed a prototype solution in a package with sides of 12 mm in height of 1 mm with a 10-nm logic, mounted top on the SoC, released in the 22-nm process technology. All this comes in one compact case. Due to the use of the basic logic, released using not the most advanced, but energy efficient process technology, the consumption of the entire chip in sleep mode was reduced to 2 mW.

According to Intel, further implementation of Moore's law can be continued only by switching to 3D packaging, which will reduce the consumption of solutions and increase if not performance, then functionality due to hybridization of processors, SoC, FPGA, accelerators and other complex logic. And this is not just a declaration, this is a plan whose implementation has already begun.



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